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? semiconductor components industries, llc, 2000 november, 2000 rev. 2 1 publication order number: mtb29n15e/d mtb29n15e preferred device power mosfet 29 amps, 150 volts nchannel d 2 pak this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers a draintosource diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls. these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 150 vdc draintogate voltage (r gs = 1.0 m w ) v dgr 150 vdc gatetosource voltage continuous nonrepetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current continuous drain current continuous @ 100 c drain current single pulse (t p 10 m s) i d i d i dm 29 19 102 adc apk total power dissipation derate above 25 c total power dissipation @ t a = 25 c (note 1.) p d 125 1.0 2.5 watts w/ c watts operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, peak i l = 29 apk, l = 1.0 mh, r g = 25 w ) e as 421 mj thermal resistance junction to case junction to ambient junction to ambient (note 1.) r q jc r q ja r q ja 1.0 62.5 50 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using the minimum recommended pad size. 29 amperes 150 volts r ds(on) = 70 m w device package shipping ordering information mtb29n15e d 2 pak 50 units/rail d 2 pak case 418b style 2 1 2 3 4 http://onsemi.com nchannel d s g marking diagram & pin assignment t29n15e yww t29n15e = device code y = year ww = work week MTB29N15ET4 d 2 pak 800/tape & reel 1 gate 4 drain 2 drain 3 source preferred devices are recommended choices for future use and best overall value.
mtb29n15e http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (v gs = 0 vdc, i d = 0.25 madc) temperature coefficient (positive) v (br)dss 150 151 vdc mv/ c zero gate voltage drain current (v ds = 150 vdc, v gs = 0 vdc) (v ds = 150 vdc, v gs = 0 vdc, t j = 125 c) i dss 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss 100 nadc on characteristics (note 2.) gate threshold voltage (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 2.0 2.7 5.4 4.0 vdc mv/ c static draintosource onresistance (v gs = 10 vdc, i d = 14.5 adc) r ds(on) 0.054 0.07 ohms draintosource onvoltage (v gs = 10 vdc) (i d = 29 adc) (i d = 14.5 adc, t j = 125 c) v ds(on) 2.4 2.1 vdc forward transconductance (v ds = 8.6 vdc, i d = 14.5 adc) g fs 10 20 mhos dynamic characteristics input capacitance (v 25 vd v 0 vd c iss 2300 3220 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss 450 630 transfer capacitance f = 1 . 0 mhz) c rss 130 260 switching characteristics (note 3.) turnon delay time t d(on) 19 40 ns rise time (v dd = 75 vdc, i d = 29 adc, v gs =10vdc t r 95 190 turnoff delay time v gs = 10 vdc, r g = 9.1 w ) t d(off) 90 180 fall time r g 9.1 w ) t f 85 170 gate charge q t 83 120 nc (v ds = 120 vdc, i d = 29 adc, q 1 12 (v ds 120 vdc , i d 29 adc , v gs = 10 vdc) q 2 37 q 3 23 sourcedrain diode characteristics forward onvoltage (i s = 29 adc, v gs = 0 vdc) (i s = 29 adc, v gs = 0 vdc, t j = 125 c) v sd 0.92 0.84 1.3 vdc reverse recovery time t rr 174 ns (i s 29 adc v gs 0 vdc t a 126 (i s = 29 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t b 48 reverse recovery stored charge di s /dt = 100 a/ m s) q rr 1.4 m c internal package inductance internal drain inductance (measured from the contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d 3.5 4.5 nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s 7.5 2. pulse test: pulse width 300 m s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperature.
mtb29n15e http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) 0 10 20 60 v ds , drain-to-source voltage (volts) figure 1. onregion characteristics i d , drain current (amps) 28 0 30 50 i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics 10 020 0 0.10 0.14 020 10 60 0.07 i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage 1.5 2.25 0 20 40 160 1 100 1000 t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) v ds 10 v t j = 100 c -55 c t j = 25 c v gs = 0 v v gs = 10 v v gs = 10 v v gs = 10 v i d = 14.5 a 35 40 60 15 v -50 -25 0 25 50 75 100 125 150 t j = 125 c 1.0 10 60 80 100 c r ds(on) , drain-to-source resistance (ohms) 012 5 4 610 30 10 40 60 0.045 0.04 0.5 0 0.1 0.02 30 25 c 3 7 t j = 25 c 8 v 9 v 4 20 25 c 30 50 40 0.05 0.055 0.06 0.065 7 v 6.5 v v gs = 10 v 5.5 v 5 v 4.5 v 4 v 89 40 50 6 v 67 0.04 0.06 0.08 0.12 t j = 100 c 25 c -55 c 50 2.0 1.75 1.25 0.75 0.25 100 120 140
mtb29n15e http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) 1000 7500 figure 7. capacitance variation -10 0 5 10 -5 15 20 25 0 2000 6000 v ds v gs 3000 5000 7000 c iss c oss c iss c rss c rss t j = 25 c v ds = 0 v v gs = 0 v 4000 1500 2500 6500 3500 5500 4500 500
mtb29n15e http://onsemi.com 5 figure 8. gatetosource and draintosource voltage versus total charge r g , gate resistance (ohms) 1 10 100 100 1 t, time (ns) t r t d(on) figure 9. resistive switching time variation versus gate resistance 120 v gs , gate-to-source voltage (volts) 20 0 0 2 0 q g , total gate charge (nc) v ds , drain-to-source voltage (volts) 10 10 20 40 t j = 25 c i d = 29 a 30 v ds v gs qt q2 q3 q1 50 1000 t f t d(off) 8 6 60 80 4 1 40 100 70 60 80 90 9 7 5 3 10 draintosource diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 15. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 0.6 0.65 0.7 0.75 0.8 0 5 10 v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) 0.85 0.95 30 v gs = 0 v t j = 25 c 15 20 25 0.9
mtb29n15e http://onsemi.com 6 i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance general data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. figure 12. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 0.1 dc 1 1000 1000 figure 13. maximum avalanche energy versus starting junction temperature 25 t j , starting junction temperature ( c) 100 200 e as , single pulse drain-to-source 75 0 50 150 100 125 300 400 avalanche energy (mj) 10 10 ms 1 ms 100 s i d = 29 a 50 150 450 250 350 10 s v gs = 20 v single pulse t c = 25 c 100 100
mtb29n15e http://onsemi.com 7 typical electrical characteristics r q ja (t) = r(t) r q ja d curves apply for power pulse train shown read time at t 1 t j(pk) - t a = p (pk) r q ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 14. thermal response t, time (seconds) r(t), effective transient thermal resistance (normalized) 1 0.1 d = 0.5 1e-05 1e-03 1e-02 1e-01 0.2 0.01 0.01 0.02 0.05 0.1 1e+00 1e+01 single pulse 1e-04 di/dt t rr t a t p i s 0.25 i s time i s t b figure 15. diode reverse recovery waveform
mtb29n15e http://onsemi.com 8 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 16. typical solder heating profile
mtb29n15e http://onsemi.com 9 package dimensions d 2 pak case 418b03 issue d style 2: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. seating plane s g d t m 0.13 (0.005) t 23 1 4 3 pl k j h v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 b m b
mtb29n15e http://onsemi.com 10 notes
mtb29n15e http://onsemi.com 11 notes
mtb29n15e http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtb29n15e/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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